SLIP 2005

Technical Program




Session 1:  Interconnect Scaling 

Ronald Ho, Sun Labs

Session 2:  Interconnect Optimization   (10:20-12:00)

Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, and Kazuya Masu

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David Albonesi, Philippe M. Fauchet, and Eby G. Friedman

J.Balachandran, S.Brebels, G.Carchon, T. Webers, W.De Raedt,B.Nauwelaers and E.Beyne

Katherine Shu-Min Li, C.-L. Lee, Yao-Wen Chang, Chauchin Su, J. E Chen

Session 3:  Interconnect Variation (1:30-2:30)

  • Dealing with Interconnect Process Variation (Invited Talk) 

NS Nagaraj, Texas Instruments

Session 4:  Interconnect Prediction (2:30-3:20)

  • Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry

Mary Y Lanzerotti, Giovanni Fiorenza, Rick A Rand

W. Heirman, J. Dambre, C. Debaes, H. Thienpont, D. Stroobandt, J. Van Campenhout

Session 5:  Power and Noise (3:50-4:50)

David Hathaway, IBM Microelectornics.



Session 6:  Interconnect in Three Dimensions (8:30-9:20)

Young-Su Kwon, Payam Lajevardi, Frank Honor´e and Anantha P. Chandrakasan

Viet H. Nguyen and Phillip Christie

Session 7:  Design Issues For Interconnect (9:40-10:40)

  • Interconnect and Current Density Stress – An Introduction to Electromigration-Aware Design (Invited Talk)

Jens Lienig, Dresden Univ.

Session 8:  Interconnect Congestion Estimation (11:00-11:50)

Chiu-Wing Sham and Evangeline F. Y. Young

Jurjen Westra and Patrick Groeneveld

CLOSING REMARKS  (11:50-12:00)



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