SLIP 2004
Technical Program
Day 1: Saturday February 14, 2004
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8:30am - 8:40am |
Welcome:
Lou Scheffer, General Chair
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8:40am - 10:00am |
Session 1: Interconnect Analysis for SoCs and Microprocessors
Moderator: Dennis Sylvester
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Invited:
"Early and Accurate Analysis of SoCs:
Oxymoron or Reality?"
Reinaldo A. Bergamaschi, IBM
"Interconnect-power
dissipation in a microprocessor"
Nir Magen, Avinoam Kolodny, Uri Weiser, Nachum Shamir, Intel
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10:00am - 10:30am |
Break
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10:30am - 12:00pm |
Session 2: Models and Metrics of Interconnect Performance
Moderator: Lou Scheffer
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"Self-consistent
Power/Performance/Reliability Analysis for Copper Interconnects"
Bipin Rajendran, Pawan Kapur, Krishna C. Saraswat, R. Fabian W. Pease,
Stanford University
"Investigation
of Performance Metrics for Interconnect Stack Architectures"
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
University of California San Diego and University of Michigan Ann Arbor
"Investigating the frequency
dependence elements of CMOS RFIC Interconnects for physical modeling"
Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jian-Guo Ma, Manh Anh
Do, Er Ping Li, Nanyang Technological University
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12:30pm - 2:00pm |
Lunch |
2:00pm - 3:30pm |
Session 3: Interconnect Design and Optimization
Moderator: Martijn Bennebroek
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"Interconnect
Width Selection for Deep Submicron Designs using the Table Lookup Method"
Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex, SPDT
Interuniversity Microelectronics Center (IMEC)
"A
Low Power Approach to System Level Pipelined Interconnect Design"
Vikas Chandra, Anthony Xu, Herman Schmit, Carnegie Mellon University
"Topology
Optimization for Application-Specific Networks-on-Chip"
Tapani Ahonen, David A. Siguenza-Tortosa, Jari Nurmi, Tampere
University of Technology
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3:30pm - 4:00pm |
Break |
4:00pm - 6:00pm |
Session 4: Interconnect in Communication Networks
Moderator: Mike Hutton
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Invited: "Evolution as the blind engineer:
wiring minimization in the brain"
Dmitri Chklovskii, Cold Spring Harbor Laboratory
"A
2-slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale
Integration (GSI)"
Ajay Joshi, Jeff Davis Georgia Institute of Technology
"NoCIC: A Spice-based
Interconnect Planning Tool Emphasizing Aggressive On-Chip Interconnect
Circuit Methods"
Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla,
Zhi Zhu, Wayne Burleson, University of Massachussetts
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Day 2: Sunday, February 15,
2004
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8:30am - 10:00am |
Session 5: Unconventional Interconnects
Moderator: Dirk Stroobandt
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Invited: "Optical solutions for system-level
interconnect"
Ian O'Connor, Ecole Centrale de Lyon
"Defect
Tolerance for Nanocomputer Architecture"
Arvind Kumar, Cornell University
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10:00am - 10:30am |
Break |
10:30am - 12:00pm |
Session 6: Statistical Interconnect Prediction
Moderator: Joni Dambre
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"Prediction
of Interconnect Adjacency Distribution: Derivation, Validation, and Applications"
Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix, Interconnect
Modeling Group, LSI Logic
"Prediction of Interconnect Net-degree Distribution
Based on Rent's Rule"
Tao Wan, Malgorzata Chrzanowska-Jeske, Portland State University
"A statistical model for estimating the effect of process variations on
crosstalk noise"
Maurizio Martina, Guido Masera, Politecnico di Torino
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12:00pm - 12:10pm |
Closing
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12:10pm - 2:00pm |
Lunch
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2:00pm - |
Group visit to the "Cité des Sciences et de
l'Industrie"
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