Day 1: Saturday April 5, 2003
9:00 am - 9:10 am	Welcome Dennis Sylvester, General Chair Lou Scheffer, Program Co-Chair
9:10 am - 10:10 am	Invited talk 1 (Chair: Lou Scheffer, Cadence, USA) Victor Kravets and Prabhakar Kudva, IBM TJ Watson Research Center, USA Understanding Metrics in Logic Synthesis for Routability Enhancement
10:10 am - 10:30 am	Break
10:30 am - 12:30 pm	Session 1: Noise and timing issues in interconnect prediction Chair: Andrew Kahng, University of California at San Diego, USA
	"Error-Correction and Crosstalk Avoidance in DSM Busses" Ketan Patel and Igor Markov (University of Michigan, USA) "Switching Activity Analysis and Pre-Layout Activity Prediction for FPGAs" Jason H. Anderson and Farid N. Najm (University of Toronto, Canada) "Sequential Budgeting with Interconnect Prediction" Chao-Yang Yeh and Marek-Sadowska Malgorzata (University of California at Santa Barbara, USA) "Placement Rent Exponent Calculation Methods, Temporal Behaviour and FPGA Architecture Evaluation" Joachim Pistorius and Mike Hutton (Altera Corp., San Jose, USA)
12:30 pm - 2:00 pm	Lunch
2:00 pm - 3:00 pm	Invited talk 2 (Chair: Payman Zarkesh-Ha, LSI Logic, USA) Martijn Bennebroek, Philips Research, The Netherlands Validation of Wire Length Distribution Models on Commercial Designs
3:00 pm - 4:30 pm	Session 2: Rent's rule analysis and congestion estimation Chair: Payman Zarkesh-Ha, LSI Logic, USA
	"Fast Estimation of the Partitioning Rent Characteristic Using a Recursive Partitioning Model" Joni Dambre, Dirk Stroobandt and Jan Van Campenhout (Ghent University, Belgium) "Perimeter-Degree: A priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement" Navaratnasothie Selvakkumaran, Phiroze Parakh and George Karypis (University of Minnesota, USA) "Accurate Pseudo-Constructive Wirelength and Congestion Estimation" Andrew B. Kahng and Xu Xu (Univ. of California, San Diego, USA)
4:30 pm - 5:00 pm	Break
5:00 pm - 6:30 pm	Session 3: Wirelength prediction Chair: Amir Farrahi, Synplicity, USA
	"Estimation of Wirelength Reduction for lambda-Geometry vs. Manhattan Placement and Routing" Hongyu Chen, C.K. Cheng, Andrew B. Kahng, Ion Mandoiu and Qinke Wang (Univ. of California, San Diego, USA) "A-Priori Wirelength and Interconnect Estimation Based on Circuit Characteristics" Shankar Balachandran, Dinesh Bhatia (University of Texas at Dallas, USA) " A Priori Interconnect Pattern Density Distribution: Derivation, Validation, and Applications" Payman Zarkesh-Ha, Peter Wright, Ken Doniger and William Loh (LSI Logic Corporation, Milpitas, USA)
Day 2: Sunday, April 6, 2003
8:30 am - 9:30 am	Invited talk 3 (Chair: Igor Markov, University of Michigan, USA) Eli Chiprout, Strategic CAD, Intel labs Bridging the gap between early physical and electrical wiring projections
9:30 am - 10:30 am	Session 4: Wirelength prediction for placement Chair: Igor Markov, University of Michigan, USA
	"Wire Length Prediction in Constraint Driven Placement" Qinghua Liu, Bo Hu and Malgorzata Marek-Sadowska (UC Santa Barbara, USA) "Maximum Multiplicity Distribution" Pranav Anbalagan and Jeff Davis (Georgia Institute of Technology, USA)
10:30 am - 10:50 am	Break
10:50 am - 12:20 pm	Session 5: Interconnect and architecture planning Chair: Dirk Stroobandt, Ghent University, Belgium
	"System Level Interconnect Design for Network-on-Chip Using Interconnect IPs" Jian Liu, Meigen Shen, Li-Rong Zheng and Hannu Tenhunen (Royal Institute of Technology (KTH), Sweden) "Global interconnect trade-off for technology over memory modules to application level: case study" A. Papanikolaou, M. Miranda, F. Catthoor, H. Corporaal, H. De Man, D. De Roest, M. Stucchi and K. Maex (IMEC, Belgium) "A Hierarchical Three-Way Interconnect Architecture for Hexagonal Processors" Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng and Ronald Graham (Univ. of California, San Diego, USA)
12:20 pm - 12:30 pm	Closing Dirk Stroobandt, Program Co-Chair
Afternoon	Lunch and whale watching trip in Monterey Bay (tentative)