Day 1: Saturday, April 6
08:00 - 08:45	Registration and Breakfast
08:45 - 08:50	Welcome from Workshop Chair Jeff Davis, Georgia Institute of Techology, USA
08:50 - 11:05	Paper session 1: Expanding Rentian analysis
	(08:50 - 09:20)  "Terminal optimization analysis for functional block re-use," S.E. Krufka and P. Christie (Univ. of Delaware, USA)  (09:20 - 09:50) "Getting more out of Donath's hierarchical model for interconnect prediction," J. Dambre, P. Verplaetse, D. Stroobandt, and J. Van Campenhout (Ghent Univ., Belgium)  (09:50 - 10:05) Break and snack  (10:05 - 10:35) "Optimized pin assignment for lower routing congestion after floorplanning phase," T. Zhang and S. Sapatnekar (Univ. of Minnesota, USA)  (10:35 - 11:05) "FPGA interconnect planning," A. Singh and M. Marek-Sadowska (UCSB, USA)
11:05 - 12:05	Invited 1
	"The X Architecture: Not your father's diagonal wiring,"  Steve Teig, Simplex Solutions, USA
12:05 - 01:15	Lunch
01:15 - 02:15	Invited 2 "Estimation needs for future networking systems interconnect"  Sudhakar Muddu, Sanera Systems, USA
02:15 - 4:30	Paper session 2: Power Grid and Signal Integrity Analysis
	(2:15 - 2:45) "Scaling trends of on-chip power distribution noise," A.V. Mezhiba and E.G. Friedman (Univ. of Rochester, USA)  (2:45 - 3:45) "Technology trends in power-grid induced noise," S.R. Nassif and O. Fakhouri (IBM Austin Research Labs and MIT, USA)  (3:45 - 4:00) Break  (4:00 - 4:30) "Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects," S. Shin, Y. Eo, and W.R. Eisenstadt (Hanyang University, Korea and Univ. of Florida, USA)
04:35 - 05:30	Invited 3 "Reconfigurable interconnect for next generation systems."  Ingrid Verbauwhede, M.F. Chang, UCLA, USA
06:30 - 07:30	Dinner
Day 2: Sunday, April 7
08:15 - 09:00	Breakfast
09:00 - 11:15	Paper session 3: Using Prediction for Performance Optimization and Estimation
	(9:00 - 9:30) "Pre-route noise estimation on interconnects of deep submicron integrated circuits," M.R. Becer, D. Blaauw, R. Panda, and I.N. Hajj , (Motorola, Univ. of Michigan, and Univ. of Illinois, USA)  (9:30 - 10:00) "Refined single trunk tree: A rectilinear Steiner tree generator for interconnect prediction," H. Chen, C. Qiao, F. Zhou, C.K. Cheng (UCSD, USA, and Synopsys,USA)  (10:00 - 10:15) Break and snack  (10:15- 10:45) "Stochastic wire length sampling for cycle time estimation," M. Iqbal, A. Sharkawy, U. Hameed, and P. Christie (Univ. of Delaware, USA)  (10:45 - 11:15) "Wire layer geometry optimization using stochastic wire sampling," R.A. Wildman, J.I. Kramer, D.S. Weile, and P. Christie (Univ. of Delaware, USA)
11:15 - noon	Invited 4 "Interconnect exploration for future wire dominated technologies"  A.Papanikolaou, M.Miranda, F.Catthoor, H.Corporaal, H.De Man, D.De Roest, M.Stucchi, K.Maex, IMEC, Belgium
12:05 - 12:05	Workshop Conclusion