Saturday, March 4, 2006
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8:30am-8:45am
WELCOME AND INTRODUCTION
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8:45am-10:15am
SESSION 1: Prediction
of Individual Wire Properties
Session Chair: Joni Dambre
(Ghent University, Belgium)
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Difficulty
of Predicting Interconnect Delay in a Timing Driven FPGA CAD Flow,
Valavan Manohararajah, Gordon
R. Chiu, Deshanand P. Singh and Stephen D. Brown (Altera Toronto
Technology Center)
|
A Priori
Prediction of Tightly Clustered Connections based on Heuristic
Classification Trees,
Pranav Anbalagan and Jeff Davis
(Georgia Tech)
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A Tale of
Two Nets: Studies of Wirelength Progression in Physical Design,
Andrew B. Kahng and Sherief
Reda (UCSD)
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10:15am-10:45am
BREAK
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10:45am-12:15pm
SESSION 2: Process
Variation
Session Chair: Ion Mandoiu (University of Connecticut,
USA)
|
An
Overview of On-chip Interconnect Variation (invited talk),
Lou Scheffer (Cadence)
|
Generation
of Design Guarantees for Interconnect Matching,
Rasit Onur Topaloglu and
Andrew B. Kahng (UCSD)
|
12:15pm-2pm
LUNCH
|
2pm-3pm
SESSION 3: Design for Manufacturability
Session
Chair: Lou Scheffer (Cadence,
USA) |
Statistical
Analysis and Optimization in the Presence of Gate and Interconnect
Delay Variations (invited talk)
Chandu Visweswariah (IBM)
|
3pm-4pm
SESSION 4: Evaluation and Prediction of FPGA
Routing Resources
Session Chair: Mike Hutton (Altera,
USA) |
Post-Placement
Interconnect Entropy: How Many Configuration Bits Does a Programmable
Logic Device Need?,
Wenyi Feng and Jonathan W.
Greene (Actel)
|
The
Routability of Multiprocessor Network Topologies in FPGAs,
Manuel Saldaña, Lesley
Shannon, and Paul Chow (University of Toronto)
|
4pm-4:30pm
BREAK
|
4:30pm-6pm
SESSION 5: Prediction and Optimization of Global
Interconnect Architectures
Session Chair: Dirk Stroobandt (Ghent University,
Belgium) |
Congestion
Modeling for Reconfigurable Interprocessor Networks,
Wim Heirman, Joni Dambre, and
Jan Van Campenhout (Gent University)
|
Modeling
and Analysis of the System Bus Latency on the SoC Platform,
Eun Ju Choi, Young Shin Cho, Je
Hoon Lee, and Kyoung Rok Cho (Chungbuk National University and
University of Southern California)
|
Energy/area/delay
Trade-offs in the Physical Design of On-chip Segmented Bus
Architectures,
Jin Guo, Antonis Papanikolaou,
Pol Marchal, and Francky Catthoor (IMEC and Katholieke
Universiteit Leuven)
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| DINNER ON YOUR OWN
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Sunday, March 5, 2006
|
9am-10:30am
SESSION 6: Physical Interconnect Analysis and
Optimization
Session Chair: Jens Lienig (Technical
University of Dresden, Germany) |
|
Impact of
Interconnect Resistance Increase on System Performance of Low Power and
High Performance Designs,
Mandeep Bamal, Youssef
Travaly, Wenqi Zhang, Michele Stucchi, and Karen Maex (IMEC and
Katholieke Universiteit Leuven) |
Statistical
Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation,
Andrew B. Kahng, Bao Liu,
Kambiz Samadi, and Xu Xu (UCSD)
|
|
Constant
Impedance Scaling Paradigm for Interconnect Synthesis,
J.Balachandran, S.Brebels,
G.Carchon, B.Nauwelers, W.de.Raedt, and E.Beyne (IMEC and
Katholieke Universiteit Leuven) |
10:30am-11am
BREAK
|
11am-12:30pm
SESSION 7: Optimal Interconnect Buffering
Session Chair: Igor Markov (University
of Michigan, USA) |
System-level
Repeater Requirements and Prediction (invited talk),
Prashant Saxena (Synopsys)
|
Minimal-Power,
Delay-Balanced Smart Repeaters for Interconnects in the Nanometer
Regime,
Roshan Weerasekera, Dinesh
Pamunuwa, LiRong Zheng and Hannu Tenhunen (KTH and Lancaster
University)
|
12:30pm-2pm
LUNCH
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| AFTERNOON SOCIAL EVENT
|
Guided walking tour of downtown Munich (English speaking
guide)
Start: Marienplatz at 2:30pm
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