SLIP'08 Technical Program
Saturday, April 5, 2008
Welcome Message | 8:45am - 9:00am |
A. Kennings (University of Waterloo)
Session 1: FPGA Interconnect Modeling and Architetectures | 9:00am - 10:00am |
Chair: Chair: Avinoam Kolodny (Technion)
Interconnection Lengths and Delays Estimation for Communication Links in FPGAs, Terrence Mak, Pete Sedcole, Peter Y.K. Cheung and Wayne Luk (Imperial College London)
Efficient Tiling Patterns for Reconfigurable Gate Arrays, Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst and Sylvain Guilley (ENST Paris and CNRS)
Break | 10:00am - 10:30am |
Session 2:Timing Optimization | 10:30am -12:00pm |
Chair: Alex Yakovlev ( Newcastle University)
Invited: Timing Optimization in Logic with Interconnect, Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar and Avinoam Kolodny (Technion and University of Rochester)
Revisiting Fidelity: A Case of Elmore-based Y-routing Trees, Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman and Parthasarathi Dasgupta ( Bengal Engineering and Science University and Indian Institute of Management Calcutta )
Lunch | 12:30pm - 2:00pm |
Session 3: Multi-Core Architectures | 2:00pm - 3:00pm |
Chair: Alex Yakovlev ( Newcastle University)
Invited: Multi-core Architectures and Streaming Applications, Gerard J.M. Smit , Andre B.J. Kokkeler, Pascal T. Wolkotte, Marcel van de Burgwal (University of Twente)
Break | 3:00pm - 3:30pm |
Session 4: High-Performance Communication Links | 3:30pm - 5:00pm |
Chair: Dirk Stroobandt (Ghent University)
Parallel vs. Serial On-Chip Communication, Rostislav Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny and Ran Ginosar (Technion)
Global Interconnections in FPGAs: Modeling and Performance Analysis, Terrence Mak, Crescenzo D'Alessandro, Pete Sedcole, Peter Y.K. Cheung, Alex Yakovlev and Wayne Luk (Imperial College London and Newcastle University)
Circuit and Physical Design of the MDGRAPE-4 On-Chip Network Links, Duraid Madina and Makoto Taiji (Tokyo University and RIKEN)
Dinner | 6:00pm - 8:00pm |
Sunday, April 6, 2007
Session 5: Interconnect Modeling and Global Routing | 9:00am - 10:00am |
Chair: Simon Moore ( University of Cambridge)
The Impact of Variability on the Reliability of Long on-chip Interconnect in the Presence of Crosstalk, Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alex Yakovlev and Gordon Russell (Newcastle University)
Sidewinder - A Scalable ILP-Based Wire Router, Jin Hu, Jarrod Roy and Igor Markov (University of Michigan)
Break | 10:00am -10:30am |
Session 6: On-Chip Communication | 10:30am - 12:00pm |
Chair: Ion Mandoiu ( University of Connecticut)
Invited: The Next Resource War: Computation vs. Communication, Simon Moore and Daniel Greenfield(University of Cambridge, UK)
Rent's Rule and Parallel Programs: Characterizing Network Traffic Behavior, Wim Heirman, Joni Dambre, Dirk Stroobandt and Jan Van Campenhout ( Ghent University )
Lunch and Social Event | 12:00pm - 6:00pm |