SLIP 2000, San Diego, California


Day 1: Saturday, April 8 
09:00 - 10:00  Breakfast 
10:00 - 10:15  Chair's Welcome
10:15 - 12:00  Embedded tutorial:
Managing Interconnect Resources, Phillip Christie (U. Delaware)
12:00 - 13:00  Lunch 
13:00 - 14:30  Session P1: Interconnect Technology Prediction
  Theoretical Limits For Signal Reflections Due To Inductance For On-chip Interconnections, D. Deschacht, F. Huret, G. Servel, E. Paleczny, and P. Kennis (C.N.R.S., France) 
  Power Supply Design Parameters Prediction For High-Performance IC Design Flows, M. Graziano, M. Delaurenti, G. Masera, G. Piccinini, and M. Zamboni (Politecnico di Torino, Italy)
Energy-Efficient High-Speed On-chip Signaling In Deep-SubMicron CMOS Technology, Imed Ben Dhaou and Hannu Tenhunen (KTH, Sweden)
14:30 - 15:00  Discussion
- D1: Measurement techniques for interconnect estimation, Dennis Sylvester (Synopsys)
15:00 - 15:30  Break 
15:30 - 16:30  Invited talk:
Performance Analysis and Technology of 3-D ICs, Krishna C. Saraswat (Stanford):
16:30 - 18:00  Session P2: System-level Prediction
 Pre-layout Estimation of Individual Wire Length, Srinivas Bodapati (UIUC) and Farid Najm (U. Toronto, Canada)
 Efficient Representation of Interconnection Length Distributions Using Generating Polynomials, Dirk Stroobandt and Herwig Van Marck (Ghent U., Belgium)
 Prediction of Interconnect Fan-out Distribution Using Rent's Rule, P. Zarkesh-Ha, J. Davis, W. Loh and J. Meindl (GA Tech)
Day 2: Sunday, April 9
07:30 - 08:30  Breakfast 
08:30 - 10:00  Session P3: Multi-layer Architectures 
 Wiring Layer Assignments with Consistent Stage Delays, Andrew B. Kahng (UCLA) and Dirk Stroobandt (Ghent U., Belgium) 
Vertical Pitch Limitations on Performance Enhancement in Bonded Three-Dimensional Interconnect Architectures, J. W. Joyner, P. Zarkesh-Ha, J. A. Davis and J. D. Meindl (GA Tech)
Cost Based Tradeoff Analysis of Standard Cell Design, Peng Li, Pranab K. Nag and Wojciech Maly (CMU) 
10:00 - 10:30  Break 
10:30 - 11:30  Invited talk:
Real-Life Aspects of IC Routing That Make Interconnect Prediction Hard, Eric Nequist and Lou Scheffer (Cadence):
11:30 - 12:30  Discussions
- D2:  Projections of Interconnect Limits and Optimal n-tier Architectures Jeff Davis (GA Tech),
- D3:, Estimation and Removal of Routing Congestion, Amir Farrahi (IBM Watson)
13:00 -  Workshop lunch at Sea World


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