Day 1: Saturday, March 31
08:00-08:30	Registration and Breakfast
08:30 - 08:35	Welcome from Workshop Chair  Phillip Christie, U. Delaware, USA.
08:35 - 09:15	Tutorial #1:
	Rent's Rule and Wire Distribution Models, Dirk Stroobandt (Ghent University, Belgium)
09:15 - 11:30	Paper Session 1: Rent's Rule Based Analysis
	-(9:15-9:45) Wirelength Estimation based on Rent Exponents of Partitioning and Placement, Xiaojian Yang, Elaheh Bozorgzadeh, and Majid Sarrafzadeh (UCLA).
	-(9:45-10:15) On Intrinsic vs. Layout Rent Properties, P. Verplaetse, J. Dambre, D. Stroobandt and J. Van Campenhout (Ghent University, Belgium).
	-(10:15-10:30) Break and snack
	-(10:30-11:00) Multi-terminal Nets do Change Conventional Wire Length Distribution Models, Dirk Stroobandt (Ghent University, Belgium).
	-(11:00-11:30) On Rents rule for rectangular regions, J. Dambre, P. Verplaetse, D. Stroobandt and J. Van Campenhout (Ghent University, Belgium).
11:30 - 12:30	Invited Talk: Are Wires Plannable? (Ralph Otten, Technical University of Eindhoven, The Netherlands)
12:30 - 01:30	Lunch
01:30 - 02:30	Tutorial #2: A Comprehensive Look at System Level Modeling (Ken Rose, Rensselaer Polytechnic Institute)
02:30 - 04:45	Paper Session 2: Interconnect Prediction and Advanced Architectures
	-(2:30-3:00) On the Relevance of Wire Load Models, Kenneth D. Boese (Cadence), Andrew B. Kahng (UCSD) and Stefanus Mantik (UCLA) (Cadence Design Systems, UCLA).
	-(3:00-3:30) Interconnect Implications of Growth-Based Structural Models for VLSI Circuits, Chung-Kuan Cheng, Andrew B. Kahng and Bao Liu (UCSD).
	-(3:30-3:45) Break
	-(3:45-4:15) Interconnect Requirement Prediction and Three-Dimensional Integration of Field-Programmable Gate Arrays, Arifur Rahman, Shamik Das, Anantha Chandrakasan, and Rafael Reif (MIT).
	-(4:15-4:45) Interconnect Complexity-Aware FPGA Placement Using Rent's Rule, G. Parthasarathy, M. Marek-Sadowska, Arindam Mukherjee, and Amit Singh (University of California at Santa Barbara).
04:45 - 05:45	Invited Talk: Interconnect Prediction for Programmable Logic Devices (Mike Hutton, Altera Corp.)
06:30 - 07:30	Dinner
Day 2: Sunday, April 1
08:00 - 08:30	Breakfast
08:30 - 09:10	Tutorial #3: Yield Modeling and BEOL Fundamentals
	(Speaker: Jose Pineda de Gyvez, Philips Research Laboratories, The Netherlands)
09:10 - 11:30	Paper Session 3: A Priori Interconnect Design Techniques
	-(9:10-9:40) Pre-layout prediction of interconnect manufacturability, Phillip Christie and Jose Pineda de Gyvez (Philips Research Laboratories)
	-(9:40-10:10) Simultaneous Signal and Power Routing Based on Interconnect Estimation, James D. Z. Ma and Lei He (University of Wisconsin).
	-(10:10-10:30) Break and Snack
	- (10:30-11:00) Hierarchical Power Supply Noise Evaluation for Early Power Grid Design Prediction, M. Graziano, G. Masera, G. Piccinini, M. Zamboni (Politecnico di Torino, Italy).
	-(11:00-11:30) An Effective Low Power Design Methodology Based on Interconnect Prediction, Shih-Hsu Huang, Mely Chen Chi, Hsu-Ming Hsiao Chung Yuan Christian University (Taiwan) and Industrial Technology Research Institutes (Taiwan)
11:30 - 12:30	Invited Talk: Rent's Rule Based Switching Requirements? (Andre' DeHon, California Institute of Technology)
12:30 - 12:35	Workshop Conclusion