The 2021 ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP) is the 23rd edition of the Workshop.
SLIP, co-located with ICCAD 2021, will bring together researchers and practitioners who have a shared interest in the challenges and futures of system-level interconnect, coming from wide-ranging backgrounds that span system, application, design and technology.
The technical goal of the workshop is to
identify fundamental problems, and,
foster new pathfinding of design, analysis, and optimization of system-level interconnects with emphasis on system-level interconnect modeling and pathfinding, DTCO-enhanced interconnect
fabrics, memory and processor communication links, novel dataflow mapping for machine learning, 2.5/3D architectures, and new fabrics for the beyond-Moore era.
Original submissions in the form of regular technical papers, invited sessions (tutorials, panels, special-topic sessions), workshop discussion topics, and posters are welcome. Program content is accepted based on novelty and contributions to the advancement of the field. Accepted technical papers will be published in the ACM and IEEE digital libraries.
Technical topics include but are not limited to:
Learning and predictive models for interconnect at various IC and system design stages
Roadmapping and pathfinding of on-chip interconnect and 2.5D/3D chip-to-chip communication interfaces
System-level design for FPGAs, NoCs reconfigurable systems, and domain-specific multi/many-core systems
Design, analysis, and (co)optimization of power, clock distribution networks, and memory partitioning systems
System-level interconnect reliability, aging, thermal, yield and cost issues
Topologies and fabrics of multi- and many-core architectures
Predictive models for power and performance of system-level interconnects
Interconnects in bio-inspired systems, such as artificial neural networks and quantum architectures
There are two special sessions this year:
3DIC architectures and high-speed interconnects
DTCO-enhanced power/clock distribution and EDA flows