UPDATE: The SLIP^2 program is online now.
Keynote addresses will be from Dr. Mustafa Badaroglu, Qualcomm and Dr. Patrick Groeneveld, Cerebras.

     

GENERAL INFORMATION

The 2020 ACM/IEEE International Workshop on System-Level Interconnect Problems and Pathfinding (SLIP^2) is the 22nd, "rebooted" edition of the System-Level Interconnect Prediction (SLIP) Workshop. As computing systems and applications grapple with a post-Moore, post-CMOS, post-von Neumann future, fundamental interconnect problems and pathfinding challenges have become more critical to address than ever before.

SLIP^2, co-located with ICCAD 2020, will bring together researchers and practitioners who have a shared interest in the challenges and futures of system-level interconnect, coming from wide-ranging backgrounds that span system, application, design and technology. The technical goal of the workshop is to (1) identify fundamental problems, and (2) foster new pathfinding of design, analysis, and optimization of interconnect and communication fabrics in electronic systems. A special emphasis is placed this year on predictive system interconnect modeling technologies, and on novel interconnect technologies and architectures for a beyond-Moore era. Additionally, a more interactive, workshop-like tone and format - recalling earlier editions of the SLIP workshop - is a goal for SLIP^2 this year.

Original submissions in the form of regular technical papers, invited sessions (tutorials, panels, special-topic sessions), workshop discussion topics, and posters are welcome. Program content is accepted based on novelty and contributions to the advancement of the field. Accepted technical papers will be published in the ACM and IEEE digital libraries.

     

TECHNICAL TOPICS

Technical topics include but are not limited to:

  • Learning and predictive models for interconnect at various IC and system design stages
  • Roadmapping and pathfinding of interconnect technology and architectures
  • Roadmapping and pathfinding of chip-to-chip interconnect, chiplets, and chip-package interfaces
  • System-level design for FPGAs, NoCs, reconfigurable systems
  • 2.5D and 3D-integrated system interconnect optimization, projection and pathfinding
  • Design, analysis, and (co)optimization of power and clock distribution networks
  • Topologies and fabrics of multi- and many-core architectures
  • Predictive models for power and performance of system-level interconnects
  • Interconnects in social, genetic, and biological systems
  • Interconnects in complex networks and high-performance computing
  • Interconnects in quantum architectures
  • System-level interconnect reliability, aging, thermal, yield and cost issues
  • Bio-inspired connectionist systems, such as artificial neural networks


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