SLIP (System Level Interconnect Prediction) News
The 21st ACM/IEEE System Level Interconnect Prediction 2019 workshop will take place at the Las Vegas Convention Center, Las Vegas, NV on June 2, 2019. It will be co-located with 56th ACM/EDAC/IEEE Design Automation Conference, June 2-6, 2019.
Attendees registering for the workshop can book a room through the DAC Hotel Reservations at discounted room rates at several hotels in the city.
Technical topics include but are not limited to:
- Learning and predictive models for optimizing interconnect at various IC and system design stages
- System-level design for FPGAs, NoCs, reconfigurable systems
- Design, analysis, and (co)optimization of power and clock networks
- Topologies and fabrics of multi- and many-core architectures
- Power consumption of interconnects
- System level reliability, aging, and thermal issues
- Security-aware power/clock delivery and interconnect design
- Design-for-manufacturing (DFM) and yield techniques for interconnects
- High speed chip-to-chip interconnect
- Design and analysis of chip-package interfaces
- 3D interconnect design and prediction
- Applications of interconnects to social, genetic, and biologicalsystems
- Emerging interconnect technologies in machine learning platforms & chips
