SLIP (System Level Interconnect Prediction) News
The 20th ACM/IEEE System Level Interconnect
Prediction 2018 workshop
will take place at the Moscone Center West, San Francisco, CA on June 23, 2018. It will be co-located with
55th ACM/EDAC/IEEE Design Automation Conference, June 24-28, 2018.
CALL For Participation: the SLIP 2018 Program is ready!
Student travel grants:
Di Gao (A Design Framework for Processing-In-Memory Accelerator)
and Jaya Dofe (Exploiting PDN Noise to Thwart Correlation Power Analysis Attacks in 3D ICs)
Attendees registering for the workshop can book a room through the DAC block at discounted room rates at several hotels in the city.
Technical topics include but are not limited to:
- Interconnect prediction and optimization at various IC and system design stages
- System-level design for FPGAs, NoCs, reconfigurable systems
- Design, analysis, and optimization of power and clock networks
- Interconnect reliability Interconnect topologies and fabrics of multi- and many-core architectures
- Design-for-manufacturing (DFM) and yield techniques for interconnects
- High speed chip-to-chip interconnect design
- Design and analysis of chip-package interfaces
- Power consumption of interconnects
- 3D interconnect design and prediction
- Applications of interconnects to social, genetic, and biological systems
- Co-optimization of interconnect technology and chip design
- Emerging interconnect technologies in machine learning platforms & chips