PROGRAM

2022 ACM/IEEE System Level Interconnect Pathfinding Workshop

Technical Program

November 3, 2022

 

8:00am - 8:05am
Welcome Message

General Chair: Mustafa Badaroglu (Qualcomm)

Technical Program Chair: Shantanu Dutt (University of Illinois at Chicago)

 

8:05am – 9:00am
Keynote

Session Chair: Mustafa Badaroglu (Qualcomm)

Computation immersed in memory through N3xt 3D MOSAIC, illusion scaleup, and co-design,
Subhasish Mitra (Stanford University)

 

9:00am – 10:00am
Breaking the interconnect limits

Session Chair: Ismail Bustany (AMD)

9:00am – 9:30am Multi-die heterogeneous FPGAs: How balanced should netlist partitioning be?
Raveena Raikar, Dirk Stroobandt (Ghent University)

9:30am – 10:00am Limiting interconnect heating in power-driven physical synthesis,
Xiuyan Zhang, Shantanu Dutt (University of Illinois at Chicago)

 

10:00am – 10:30am Coffee Break

 

10:30am – 12:00pm
2.5D/3D extension for high-performance computing

Session Chair: Pascal Vivet (CEA)

10:30am – 11:15am How to design thousand chiplet systems?
Puneet Gupta (UCLA) - invited

11:15am – 12:00pm Opportunities of chip power integrity and performance improvement through wafer backside connection,
Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van Der Plas, Eric Beyne (IMEC) - invited

 

12:00pm – 1:00pm Lunch

 

1:00pm – 1:55pm
Keynote

Session Chair: Shantanu Dutt (University of Illinois at Chicago)

A SRAM-based CIM AI accelerator for smart edge devices,
Ren Li (Qualcomm)

 

1:55pm – 2:55pm
Compute-In-Memory and design of structured compute arrays

Session Chair: Shantanu Dutt (University of Illinois at Chicago)

1:55pm – 2:25pm An automated design methodology for computational SRAM dedicated to highly data-centric applications,
Jean-Philippe Noel (CEA) - invited

2:25pm – 2:55pm A machine learning approach for accelerating SimPL-based global placement for FPGA’s,
Tianyi Yu2, Nima Karimpour Darav1, Ismail Bustany1, Mehrdad Eslami Dehkordi1 (1AMD, 2University of Toronto)

 

3:00pm – 3:30pm Coffee Break

 

3:30pm – 4:30pm
Interconnect performance estimation techniques

Session Chair: Rasit Topaloglu (IBM)

3:30pm – 4:00pm Neural network model for detour net prediction
Jaehoon Ahn, Taewhan Kim (Seoul National University)

4:00pm – 4:30pm Machine-learning based delay prediction for FPGA technology mapping,
Hailiang Hu2, Fan Zhang1, Ismail Bustany1, Bing Tian1, Jiang Hu2 (1AMD, 2Texas A&M University)

 

4:30pm – 4:35pm
Closing Remarks

Session Chair: Mustafa Badaroglu (Qualcomm)