WORKSHOP AGENDA
MORNING
08:40-08:50
08:50-10:30
Chiplet and 3D Integration
- Hybrid Bonding: Capabilities, Challenges, & Potential
Thomas Workman, Adeia
- Scaling the Memory Barrier: A Shift to 3D SRAM Design
Aditya Iyer, Georgia Tech University
- Optimizing Chiplet and Interposer Design Through AI-Driven Bump Pitch Sensitivity Analysis
Seungmin Woo, Georgia Tech University
- 3D Spiking Transformer Accelerators
Boxun Xu, UC Santa Barbara
10:30-11:00 Coffee Break
11:00-12:15
EDA and Physical Design
- Interconnect Modeling for 3DIC
Kenneth Larsen, Synopsys
- Floorplanning in the Age of AI: Challenges and Opportunities
Uday Mallappa, Intel
- Noise-aware Circuit Clustering based on Analytical Placement Evolution
Zhiyuan Chen, University of California, San Diego
12:15-13:15 Lunch Break
AFTERNOON
13:15-14:00
KEYNOTE
- Engineering the Future of IC Design with AI
Ruchir Puri, IBM
14:00-14:50
Interconnect Technology and Heterogeneous Integration
- Distributed On-chip Power Delivery for Heterogeneous Integrated Systems
Eby Friedman, University of Rochester
- The On-Chip (BEOL) Portion of System-Level Interconnects
Daniel Edelstein, IBM
14:50-15:20
Panel
- How to Break the Interconnect Redbrick Wall for the AI Era?
Daniel Edelstein, IBM, US, Eby Friedman, University of Rochester, US, Kenneth Larsen, Synopsys, US, Thomas Workman, Adeia, US
15:20-15:45 Coffee Break
15:45-17:00
Global Routing
- GPU Acceleration for Global Routing
Shiju Lin, Chinese University of Hong Kong
- The Influence of Interconnection Complexity on the FPGA CAD Flow
Xiaoke Wang, Ghent University
- Routing in 2.5D FPGAs: How Long Should Interposer Lines be?
Raveena Raikar, Ghent University
17:00-17:05