Dr. Tanay Karnik


"Recent advances and future challenges in 2.5D/3D heterogeneous integration"

Abstract In this presentation, we will review the recent advances in chiplet-based commercial products and prototypes. Most chiplet usage has been confined to integrating die designed by the same organization applied to building chips for the same product types. The right approach should be able to reduce portfolio costs, scale innovation and improve time to solution. It is important to manage the associated trade-offs, such as thermal, power, I/O escapes, assembly, test, etc. We will conclude the talk by presenting the future 2.xD/3D integration opportunities becoming available.

Biography Dr. Tanay Karnik is a Senior Principal Engineer and Director of Heterogeneous Platforms Lab of Intel Labs. Previously he was the Director of Intel's University Research Office. He received his Ph.D. in Computer Engineering from UIUC and joined Intel in 1995. His research interests are in the areas of heterogeneous integration, small form factor systems, 3D architectures, variation tolerance, power delivery and architectures for novel devices. He has published over 90 technical papers, has 95 issued and 35 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several keynotes, invited talks and tutorials, and has served on 7 PhD students' committees. He was a member of ISSCC, DAC, ICCAD, ICICDT, ISVLSI, ISCAS, 3DIC and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was General Chair of ISLPED'14, ASQED’10, ISQED'09, ISQED'08 and ICICDT'08. Tanay is an IEEE Fellow, an ISQED Fellow, an Associate Editor for TVLSI, a Senior Advisory Board Member of JETCAS and a Guest Editor for JSSC.