INVITED TALKS

Dr. Suresh Ramalingam

Prof. Makoto Nagata

Dr. Joris Van Campenhout

Yvain Thonnart

Dr. Bapi Vinnakota

Dr. Tiago Mück

Xilinx Inc., USA

Kobe University, Japan

imec, Belgium

CEA-LIST, France

ODSA, USA

Arm, USA

"Enabling chiplet integration beyond 7nm"

"Chip stacking and packaging technology explorations for hardware security"

"Silicon photonics technology for terabit-scale optical I/O"

"Designing a multi-chiplet manycore system using the POPSTAR optical NoC architecture"

"The open domain-specific architecture: An introduction"

"Network-on-Chips for future 3D stacked dies"

Abstract For several decades, microelectronic industries and relevant academic communities have invested tremendous effort in developing electronics to introduce many breakthroughs and revolutions in packaging technologies and repetitive efforts to address traditional problems. In recent years, slowdown in Moore’s law scaling and the challenging economics associated with adopting new silicon nodes has led to an industry emphasis on chiplet-based architectures that require advanced packaging options ranging from MCM to CoWoS® for HPC, Networking, Cloud Services, Emulation and other applications. Advanced heterogeneous packaging based on 2.5D CoWoS®/3D/Fan-out/Optical or other platforms are required to address various Logic and memory integration. The inexorable push towards higher performance “system in package” solutions coupled with silicon technology scaling and cost challenges is expected to stretch the heterogeneous packaging boundaries much further. Thermal solution is also becoming an active area of focus as the power levels are expected to push well beyond 500W. In this presentation, we will examine latest heterogeneous packaging industry trends, challenges and considerations from a product perspective. Heterogeneous integration of chiplet or stacked dies in a single package, leads to ever-increasing localization of heat and thermo-mechanical reliability challenges with the package and board integration. We will also touch upon some of trends and challenges in these areas and interplay with the package.

Abstract A variety of physical attacks may compromise the security of cryptographic operations. Electromagnetic (EM) and power current traces of an IC chip deliver secret information to some extent, as known as side-channel (SC) leakage, since they are strongly correlated with internal toggling among digital logic cells. The EM and laser irradiation intentionally induce bit-level faults, which may effectively reduce the search space of secret information. Advanced packaging techniques, including 2.5D IC chip packaging and 3D IC chip stacking, provide the opportunity to gain the higher level of protection against physical attempts by an adversary. The Si substrate of any IC chip can become the easiest attack surface, how ever, which is prevented by exploiting backside buried metal (BBM) wirings. The Si BBM and 3D chip stack structures have been combined for IC chip performance and SC leakage mitigation. We will discuss measurements and analysis on fabricated demonstrators of cryptographic functionality, where the capacitances at inter-tier interfaces and shields on the topmost tier exhibit prominent effects against SC leakages.

Abstract We discuss imec's Silicon Photonics interposer technology targeting Tb/s/mm2-scale Optical I/O interconnects for next-generation datacenter network switches and HPC/AI systems. We will cover recent progress in active photonic components, including high-speed Si ring modulators and GeSi electro-absorption modulators. We will also discuss the integration of high-speed Through-Silicon Vias (TSV) implemented in this platform, and illustrate how flip-chip integration with FinFET CMOS through Cu micro-bumps can enable ultra-low power Tb/s/mm2 transceivers.

Abstract Close integration of control electronics with 3D assembly of photonics and CMOS opens the way to high-performance computing architectures partitioned in chiplets connected by optical NoC on silicon photonic interposers. In this talk, we give an overview of our works on optical links and NoC for manycore systems. We leverage the POPSTAR optical NoC topology and architecture to design a 4-chiplet manycore system with associated electro-optical control electronics for optical drivers, flow-control and arbitration.

Abstract The Open Domain-Specific Architecture (ODSA) is a sub-project within the Open Compute project that aims to enable the easy development of chiplet-based designs for domain-specific accelerators. The ODSA aims to define an open physical and logical die-to-die interface, develop chiplet prototypes and establish open workflows for chiplet-based products to ultimately enable a chiplet marketplace. Product designers can then assemble domain-specific accelerators by combining best-in-class chiplets from multiple vendors. This talk will provide an overview of the ODSA, review recent progress in interfaces and prototypes and summarize its readiness for production use.

Abstract Current infrastructure SoCs, such as Arm Neoverse based platforms, provide a large number of cores (e.g. 64-128 cores) integrated using one or more large mesh-based topologies (e.g. 8x8 meshes). Future SoCs are expected to grow even larger both in terms of number of cores and mesh size (10x10 and beyond). These large meshes, however, introduce longer memory access and core-core communication latency, as well as a tendency for congestion hotspots in heavy traffic scenarios. Meanwhile, advances in 3D integration technologies create a new design space to explore 3D interconnect solutions that allow us to address these problems. In this talk we will discuss new 3D NoC topologies for 3D stacked dies as well as flat 2D topologies with express links (XL). XLs (based on the concepts Ruche Networks can leverage the wiring capabilities on additional layers in a 3D SoC to create long-range physical channels between non-adjacent tiles in the same dimension in the mesh. XLs can increase the available bandwidth and provide latencies comparable to smaller mesh topologies.

Biography Dr. Suresh Ramalingam graduated in 1994 with a Ph.D. in Chemical Engineering from Massachusetts Institute of Technology, Cambridge. He holds 40 US Patents, 30+ publications, 2013 SEMI Award, Ross Freeman Award for Technical Innovation, ECTC 2011 Conference Best Paper Award, IMAPS 2013 and 2014 Conference Best Paper Awards for 2.5D/3D and contributed a book chapter on 3D Integration in VLSI Circuits. He started his career at Intel developing Organic Flip Chip Technology for Micro-processors which was implemented on Pentium II (Intel's first flip chip product) in 1997. The effort received personal recognition from then CEO Craig Barrett. As one of the co-founders and Director of Packaging Materials at Scion Photonics started in 2000, he helped develop DWDM modules used by major communication companies. JDS Uniphase acquired Scion Photonics in 2002. After joining Xilinx in 2004, he has experienced various roles from Substrate Technology & Sourcing, Design Management to Packaging Technology Development. As a Xilinx Fellow, he currently manages Advanced Packaging Interconnect Technology Development including TSV/3D/Optical for Xilinx FPGA products. Thermal and Mechanical Enablement at Board/System Level is a key focus area to push the power/performance envelope and this is an area he currently manages for Xilinx Alveo and SOM products.

Biography Prof. Makoto Nagata is a professor of the graduate school of science, technology and innovation, Kobe University, Japan. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (ISSCC) since 2018. He served as a technical program chair (2010-2011), symposium chair (2012-2013) and an executive committee member for the Symposium on VLSI circuits. He is currently an AdCom member to the IEEE Solid-State Circuits Society and also serves as a distinguished lecturer (DL) in the society, both since 2020. He is an associate editor for IEEE Transactions on VLSI Systems.

Biography Dr. Joris Van Campenhout is Fellow Silicon Photonics and Director of the industry-affiliation R&D program on Optical I/O, which seeks to substantially scale optical interconnects to bandwidth densities beyond 1Tbps/mm, while consuming less power than 1pJ/bit. Prior to joining imec in 2010, Joris was a post-doctoral researcher at IBM's TJ Watson Research Center (USA), where he developed silicon electro-optic switches, and he obtained a PhD degree in Electrical Engineering from Ghent University (Belgium) in 2007, for his work on heterogeneous integration of III-V lasers on silicon. Joris has authored or co-authored 12 patents and over 100 papers in the field of silicon integrated photonics, which have received 10000+ citations.

Biography Yvain Thonnart graduated as an engineer from Ecole Polytechnique and Telecom Paris, France. He then joined the Technological Research Division of CEA, the French Alternative Energies and Atomic Energy Commission, within the CEA-Leti institute until 2019, then within the CEA-List institute. He is now senior expert on communication and synchronization in systems on chip, and scientific advisor for the mixed-signal design lab. His main research interests include asynchronous logic, networks on chip, physical implementation, emerging technologies integration such as photonics, cryoelectronics and interposers.

Biography Dr. Bapi Vinnakota leads the Open Domain-Specific Architecture sub-project, in the Open Compute Project. The ODSA has active volunteers from over 50 companies and aims to define an open chiplet marketplace.

Biography Dr. Tiago Mück received his M.Sc. in Computer Science from the Federal University of Santa Catarina (UFSC) in 2013 and his PhD from the University of California, Irvine (UCI) in 2018. Since then, he has been a research engineer at Arm working on scalable system software and computer architecture. He is specially interested in cross-layer hardware/software co-design issues, heterogeneous architectures, high performance computing systems, network-on-chips, and OS support for energy efficient multi/many core systems.