| Thomas Workman |
Adeia |
Hybrid Bonding: Capabilities, Challenges, & Potential |
| Aditya Iyer |
Georgia Tech University |
Scaling the Memory Barrier: A Shift to 3D SRAM Design |
| Seungmin Woo |
Georgia Tech University |
Optimizing Chiplet and Interposer Design Through AI-Driven Bump Pitch Sensitivity Analysis |
| Boxun Xu |
UC Santa Barbara |
3D Spiking Transformer Accelerators |
| Kenneth Larsen |
Synopsys |
Interconnect Modeling for 3DIC |
| Uday Mallappa |
Intel |
Floorplanning in the Age of AI: Challenges and Opportunities |
| Zhiyuan Chen |
University of California, San Diego |
Noise-aware Circuit Clustering based on Analytical Placement Evolution |
| Eby Friedman |
University of Rochester |
Distributed On-chip Power Delivery for Heterogeneous Integrated Systems |
| Daniel Edelstein |
IBM |
The On-Chip (BEOL) Portion of System-Level Interconnects |
| Shiju Lin |
Chinese University of Hong Kong |
GPU Acceleration for Global Routing |
| Xiaoke Wang |
Ghent University |
The Influence of Interconnection Complexity on the FPGA CAD Flow |
| Raveena Raikar |
Ghent University |
Routing in 2.5D FPGAs: How Long Should Interposer Lines be? |