XXI Century Gigascale Integration (GSI) : The Interconnect
From the inception of microelectronics in 1959 until the early 1990's,
transistors dominated both the performance and cost of microchips
while interconnects were of secondary importance. In recent years,
this hegemony has reversed itself. Interconnects now tend to
dominate microchip performance and cost with transistors relegated to the
secondary role. To appreciate the epical nature of this
shift, consider the following illustration of the interconnect
problem. For late 1980's 1.0 m technology, the intrinsic
switching delay of an unloaded MOSFET approaches 10 ps while the response
time of a 1.0 mm interconnect is approximately 1 ps. But, for early
2000's 0.1 m technology, the intrinsic delay of a MOSFET
decreases to about 1.0 ps while the response time of a 1.0 mm
interconnect increases to 100 ps. Interconnect latency
devolves from one decade faster to two decades slower than
transistor delay! Concurrent with this signal wiring
dilemma, clock frequency is increasing by 100X placing stringent new
demands on the chip clock distribution network. Supply current is
increasing by 60X while supply voltage scales downward by 80% thereby
imposing a huge new burden on the power distribution network.
Maximum total wire length per chip increases by 50X. And,
chip pad or input/output interconnect count increases by 10X.
James D. Meindl
The profound and pervasive nature of the interconnect problem
demands a commensurate response. The central thesis of
this response is that early XXI century opportunities for
GSI will be governed by an interconnect dominated hierarchy of
theoretical and practical limits whose five levels are codified as
fundamental, material, device, circuit and system.
Systematic exploration of this hierarchy of limits reveals salient
opportunities for addressing the interconnect problem.