SLIP'09 Technical Program

Sunday, July 26, 2009  

Room 306 - South Lobby (Esplanade Area) - Moscone Center  

Welcome Message + Keynote Speech 8:45am - 9:45am

Bill Bottoms  
"Interconnect Solutions for TeraScale Computing"

Coffee Break 9:45am - 10:00am
Session 1: New Frontiers for Interconnect Prediction Techniques 10:00am - 12:00pm

Session Chair: D. Chen

Honeycomb-Structured Computational Interconnects and Their Scalable Extension to Spherical Domains
Joseph Cessna and Thomas Bewley

OIL: A Nanophotonic Optical Interconnect Library for a New Photonic Networks-on-Chip Architecture
Duo Ding and David Z. Pan

Closed-Form Solution for Timing Analysis of Process Variations on SWCNT Interconnect
Peng Sun and Rong Luo

Is Overlay Error More Important Than Interconnect Variations in Double patterning?
Kwangok Jeong, Andrew Kahng and Rasit Topaloglu

Using Circuit Structural Analysis Techniques for Networks in Systems Biology
Sherief Reda

Discussion Panel - Panelists: D. Chen, D. Stroobandt, and Yu Cao

Lunch 12:00pm - 1:15pm
Session 2: New Advances in Classical Interconnect Prediction Techniques 1:15pm -2:50pm

Session Chair: C. K. Cheng

A Pre-Placement Net Length Estimation Technique for Mixed-Size Circuits
Bahareh Fathi, Laleh Behjat and Logan Rakai

Floorplan-based FPGA Interconnect Power Estimation in DSP circuits
Ruzica Jevtic, Carlos Carreras and Vukasin Pejovic

Prediction of High-Performance On-Chip Global Interconnection
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James Buckwalter and Chung-Kuan Cheng

On the Bound of Time-Domain Power Supply Noise Based on Frequency-Domain Target Impedance
Xiang Hu, Wenbo Zhao, Yulei Zhang, Amirali Shayan, A. Ege Engin and Chung-Kuan Cheng

Discussion Panel - Panelists: P. Zarkesh-Ha, C. K. Cheng and Sung Kyu Lim

Coffee Break 2:50pm - 3:10pm
Session 3: Interconnect Prediction for 3D ICs 3:10pm - 4:45pm

Session Chair: J. Wang

From 3D Circuit Technologies and Data Structures to Interconnect Prediction (Invited)
Robert Fischbach and Jens Lienig

Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs
Dae Hyun Kim, Saibal Mukhopadhyay and Sung Kyu Lim

Predicting the Worst-Case Voltage Violation in a 3D Power Network
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan, A. Ege Engin and Chung-Kuan Cheng

Integrated Interlayer Via Planning and Pin Assignment for 3D ICs
Xu He, Sheqin Dong, Xianlong Hong and Saroshi Goto

Discussion Panel - Panelists: J. Wang, D. Pan and S. Reda

Break 4:45pm - 5:00pm
Panel: Impact of Emerging Interconnect Technologies on SLIP Research Directions 5:00pm - 6:30pm

Moderator: D. Chen

Nanomaterials for VLSI Interconnect and Energy-Storage Applications
K. Banerejee

Multiband RF-Interconnect for Reconfigurable Network-on-Chip Communications
J. Cong

Carbon Nanotube, Graphene and Atomic Wires as Next Generation Interconnects: Current Status and Future Promise
S. Nayak

Performance Comparison of Cu/Low-K, Carbon Nanotube, and Optics for On-chip and Off-chip Interconnects
K. Saraswat

Transfer to banquet dinner location 6:30pm - 7:30pm
Dinner + Future prediction by attendees 7:30pm - 9:45pm